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INTEGRATED CIRCUITS
74LV259 8-bit addressable latch
Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 May 20
Philips Semiconductors
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
FEATURES
* Optimized for low voltage applications: 1.0 to 3.6 V * Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V * Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, * Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, * Combines demultiplexer and 8-bit latch * Serial-to-parallel capability * Output from each storage bit available * Random (addressable) data entry * Easily expandable * Common reset input * Useful as a 3-to-8 active HIGH decoder * Output capability: standard * ICC category: MSI
Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV259 is a low-voltage CMOS device and is pin and function compatible with 74HC/HCT259. The 74LV259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. The 74LV259 is a multifunction device capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The 74LV259 also incorporate an active LOW common reset (MR) for resetting all latches, as well as an active LOW enable input (LE). The 74LV259 has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the D input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and date (D) input. When operating the 74LV259 as an addressable latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table summarizes the operations of the 74LV259.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf 2.5 ns SYMBOL PARAMETER Propagation delay D, An to Qn LE to Qn MR to Qn Input capacitance Power dissipation capacitance per latch VI = GND to VCC1 CONDITIONS CL = 15 pF; VCC = 3.3 V TYPICAL 17 16 14 3.5 19 UNIT
tPHL/tPLH CI CPD
ns
pF pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV259 N 74LV259 D 74LV259 DB 74LV259 PW NORTH AMERICA 74LV259 N 74LV259 D 74LV259 DB 74LV259PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1
1998 May 20
2
853-1988 19420
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
PIN CONFIGURATION
A0 A1 A2 Q0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC MR LE D Q7 Q6 Q5 Q4
PIN DESCRIPTION
PIN NUMBER 1, 2, 3 4, 5, 6, 7, 9, 10, 11, 12 8 13 14 15 16
SV01602
SYMBOL A0 to A2 Q0 to Q7 GND D LE MR VCC
FUNCTION Address inputs Latch outputs Ground (0 V) Data input Latch enable input (active LOW) Conditional reset input (active LOW) Positive supply voltage
LOGIC SYMBOL
14 LE 13 D
LOGIC SYMBOL (IEEE/IEC)
15 13 Q0 Q1 Q2 Q3 4 5 6 7 9 10 3 11 12 4 5 15 9 10 11 12 1 2 3 14 2 0 0 G 7 G8 Z9 DX 0 9, 10D 1 C10 8R 4
1 2
5 6 7
1 2 3
A0 A1 A2 MR
Q4 Q5 Q6 Q7
SV01601
6 7
SV01603
FUNCTIONAL DIAGRAM
Q0 1 A0 2 A1 3 A2 8 LATCHES Q4 14 LE 15 MR 13 D Q5 Q6 Q7 9 10 11 12 1-of-8 DECODER Q1 Q2 Q3 4 5 6
MODE SELECT TABLE
LE L H L H
7
MR H H L L Addressable latch Memory
MODE
Active HIGH 8-channel demultiplexer Reset
SV01604
1998 May 20
3
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
FUNCTION TABLE
INPUTS OPERATING MODES Master reset MR L L L L Demultiplex (active HIGH) ( ) decoder (when D = H) L L L L L Store (do nothing) H H H H H Addressable latch H H H H LE H L L L L L L L L H L L L L L L L L D X d d d d d d d d X d d d d d d d d A0 X L H L H L H L H X L H L H L H L H A1 X L L H H L L H H X L L H H L L H H A2 X L L L L H H H H X L L L L H H H H Q0 L Q=d L L L L L L L q0 Q=d q0 q0 q0 q0 q0 q0 q0 Q1 L L Q=d L L L L L L q1 q1 Q=d q1 q1 q1 q1 q1 q1 Q2 L L L Q=d L L L L L q2 q2 q2 Q=d q2 q2 q2 q2 q2 OUTPUTS Q3 L L L L Q=d L L L L q3 q3 q3 q3 Q=d q3 q3 q3 q3 Q4 L L L L L Q=d L L L q4 q4 q4 q4 q4 Q=d q4 q4 q4 Q5 L L L L L L Q=d L L q5 q5 q5 q5 q5 q5 Q=d q5 q5 Q6 L L L L L L L Q=d L q6 q6 q6 q6 q6 q6 q6 Q=q q6 Q7 L L L L L L L L Q=d q7 q7 q7 q7 q7 q7 q7 q7 Q=d
NOTES: H = HIGH voltage level L = LOW voltage level X = don't care d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition q = lower case letters indicate the state of the referenced output established during the last cycle established during the last cycle in which it was addressed or cleared
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage Input voltage Output voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V CONDITIONS See Note 1 MIN 1.0 0 0 -40 -40 - - - - - - TYP 3.3 - - MAX 3.6 VCC VCC +85 +125 500 200 100 UNIT V V V C ns/V
Input rise and fall times
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
1998 May 20
4
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC "IIK "IOK "IO "IGND, "ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with - standard outputs Storage temperature range Power dissipation per package - plastic DIL - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12 mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +4.6 20 50 25 UNIT V mA mA mA
50 -65 to +150 750 500 400
mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2 V VIH HIGH level Input l lI t voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V VIL LOW level Input l lI t voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V; VI = VIH or VIL; -IO = 100A VO OH HIGH level output voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; -IO = 100A VCC = 2.7 V; VI = VIH or VIL; -IO = 100A VCC = 3.0 V; VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; -IO = 6mA VCC = 1.2 V; VI = VIH or VIL; IO = 100A VO OL LOW level output voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; IO = 100A VCC = 2.7 V; VI = VIH or VIL; IO = 100A VCC = 3.0 V; VI = VIH or VIL; IO = 100A VOL LOW level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; IO = 6mA 1.8 2.5 2.8 2.40 1.2 2.0 2.7 3.0 2.82 0 0 0 0 0.25 0.2 0.2 0.2 0.40 0.2 0.2 0.2 0.50 V V 1.8 2.5 2.8 2.20 V V 0.9 1.4 2.0 0.3 0.6 0.8 -40C to +85C TYP1 MAX -40C to +125C MIN 0.9 1.4 2.0 0.3 0.6 0.8 V V MAX UNIT
1998 May 20
5
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
DC ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER Input leakage current Quiescent supply current; MSI Additional quiescent supply current per input TEST CONDITIONS MIN II ICC ICC VCC = 3.6 V; VI = VCC or GND VCC = 3.6 V; VI = VCC or GND; IO = 0 VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V -40C to +85C TYP1 MAX 1.0 20.0 500 -40C to +125C MIN MAX 1.0 160 850 A A A UNIT
NOTE: 1. All typical values are measured at Tamb = 25C.
AC CHARACTERISTICS
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 tPHL/tPLH / Propagation delay g y D to Qn Figure 2 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH / Propagation delay g y An to Qn Figure 3 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH / Propagation delay g y LE to Qn Figure 1 2.0 2.7 3.0 to 3.6 1.2 tPHL Propagation delay g y MR to Qn Figure 4 2.0 2.7 3.0 to 3.6 2.0 tw LE pulse width l idth HIGH or LOW Figure 1 2.7 3.0 to 3.6 2.0 tw MR pulse width l idth LOW Figure 4 2.7 3.0 to 3.6 1.2 tsu Set-up time D, An to LE Figure 5 and 6 2.0 2.7 3.0 to 3.6 1.2 th Hold time D to LE Figure 5 2.0 2.7 3.0 to 3.6 5 5 5 24 18 14 34 25 20 34 25 20 MIN LIMITS -40 to +85 C TYP1 105 36 26 202 105 36 26 202 100 34 25 192 90 31 23 172 10 8 62 10 8 62 35 12 9 72 -30 -10 -8 -62 5 5 5 ns 29 21 17 ns 43 31 25 41 30 24 41 30 24 ns ns 53 39 31 ns 48 35 28 60 44 35 ns 49 36 29 61 45 36 ns 49 36 29 61 45 36 ns MAX -40 to +125 C MIN MAX UNIT
1998 May 20
6
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
AC CHARACTERISTICS (Continued)
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 th Hold time An to LE Figure 6 2.0 2.7 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C 2. Typical values are measured at VCC = 3.3 V. 5 5 5 MIN -40 to +85 C TYP1 -20 -7 -5 -42 5 5 5 ns MAX -40 to +125 C MIN MAX UNIT
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V and 3.6V; VM = 0.5 x VCC at VCC < 2.7 V and 4.5 V. VOL and VOH are the typical output voltage drop that occur with the output load.
VCC Dn INPUT GND VOH Qn OUTPUT VM tW tPHL VOH Qn OUTPUT VOL VM VCC tPLH VOL VM VCC An INPUT GND tPHL tPLH VM
VCC LE INPUT GND
SV01607
Figure 3. Address inputs (An) to output (Qn) propagation delays.
SV01605
MR INPUT GND
VM
Figure 1. Enable input (LE) to output (Qn) propagation delays and the enable input pulse width.
tW tPHL
VCC Dn INPUT GND tPHL VOH Qn OUTPUT VOL VM tPLH VM
VOH Qn OUTPUT VOL VM
SV001606
Figure 4. Conditional reset input (MR) to output (Qn) propagation delays.
SV01608
Figure 2. Data input (D) to output (Qn) propagation delays.
1998 May 20
7
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
AC WAVEFORMS (Continued)
VM = 1.5 V at VCC 2.7 V and 3.6V; VM = 0.5 x VCC at VCC < 2.7 V and 4.5 V. VOL and VOH are the typical output voltage drop that occur with the output load.
VCC LE INPUT GND tsu th VCC Dn INPUT GND VOH Qn OUTPUT VOL The shaded areas indicate when the input is permitted to change for predictable output performance Q=D VM Q=D VM tsu th VM
TEST CIRCUIT
VCC S1 2 * VCC Open GND
1k VI PULSE GENERATOR RT D.U.T. VO
50pF
CL
1k
DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
TEST tPLH/tPHL S1 Open VCC < 2.7V 2.7-3.6V VI VCC 2.7V
SV01609 SV00905
Figure 5. Data set-up and hold times for D input to LE input. Figure 7. Load circuitry for switching times.
VCC An INPUT GND tsu VCC LE INPUT GND The shaded areas indicate when the input is permitted to change for predictable output performance. SV01610 VM th VM ADDRESS STABLE
Figure 6. Address set-up and hold times for An inputs to LE input.
1998 May 20
8
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1998 May 20
9
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1998 May 20
10
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
1998 May 20
11
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
1998 May 20
12
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
NOTES
1998 May 20
13
Philips Semiconductors
Product specification
8-bit addressable latch
74LV259
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04442
Philips Semiconductors
1998 May 20 14

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